An integrated circuit is a network of circuit elements such as resistors, capacitors, inductors, mutual inductors, transmission lines, diodes, bipolar junction transistors (BJT), junction field effect transistors (JFET), metal-oxide-semiconductor field effect transistors (MOSFET), metal-semiconductor field effect transistors (MESFET), thin-film transistors (TFT), etc.
The development of complicated integrated circuits often requires the use of powerful numerical simulation programs. For example, circuit simulation is an essential part in the design flow of integrated circuits, helping circuit designers to verify the functionality and performance of their designs without going through expensive fabrication processes. As the semiconductor processing technology migrates to nanometer dimensions, new simulation methodologies are needed to solve the new problems intrinsically existing in circuit design with nanometer features. Modern integrated circuits continually challenge circuit simulation algorithms and implementations in the development of new technology generations. The semiconductor industry requires EDA software with the ability to analyze nanometer effects like coupling noise, ground bounce, transmission line wave propagation, dynamic leakage current, supply voltage drop, and nonlinear device and circuit behavior, which are all related to dynamic current. Thus, detailed circuit simulation and transistor-level simulation have become one of the most effective ways to investigate and resolve issues with nanometer designs.
Examples of electronic circuit simulators include the Simulation Program with Integrated Circuit Emphasis (SPICE) developed at the University of California, Berkeley (UC Berkeley), and various enhanced versions or derivatives of SPICE. SPICE and its derivatives or enhanced versions will be referred to hereafter as SPICE circuit simulators, or SPICE. The SPICE method considers a circuit as a non-divided object.
SPICE-like simulations may provide fairly accurate predictions of how corresponding circuits will behave when actually built. The predictions are preferably made not only for individual sub-circuit but also for whole systems (e.g., whole integrated circuits) so that system-wide problems relating to noise and the like may be uncovered and dealt with. In a general process flow of a SPICE-like simulation, an analog integrated circuit under simulation is often represented in the form of a netlist description. A netlist is a circuit description of the analog circuit to be simulated written in a SPICE-like language. SPICE netlists are pure structural languages with simulation control statements. Other language like Verilog-A™ has the capability to include behavioral constructs. The structural netlist of SPICE together with a predefined set of circuit components of the analog integrated circuit may be represented in the form of a matrix in accordance with certain circuit modeling methodologies. The number of non-linear differential equations ranges from 1 to n. There are a corresponding number of input vectors to be operated by the linear equation. The set of input vectors are shown as {I1, I2, . . . In}. Next, the linear matrix is computed with the set of input vectors to generate a set of solution vectors {V1, V2, . . . Vn}. The computation is repeated until the set of solutions converge. The set of solutions may be then displayed in the form of waveforms, measurements, or checks on a computer screen for engineers to inspect the simulation results.
However, SPICE-like simulation of a whole system becomes more difficult and problematic as the industry continues its relentless trek of scaling down to smaller and smaller device geometries and of cramming more interconnected components into the system. An example of such down scaling is the recent shift from micron-sized channels toward deep submicron sized transistor channel lengths. Because of the smaller device geometries, a circuit designer are able to cram exponentially larger numbers of circuit components (e.g., transistors, diodes, capacitors) into a given integrated circuit (IC), and therefore increases the system to millions of devices. FIG. 1A illustrates an example of such system that may contain millions of devices. As shown in FIG. 1A, the memory circuit includes 64,000 repetitive columns 102, each of the columns includes 512 repetitive rows and each row is represented by a row branch circuit 104 which in turn calls to a leaf circuit 106. All 512 repetitive rows in the column are connected together through a node 108, and each node is driven by a sense amplifier 110.
One approach to represent the increasingly complex system is to use a hierarchical system as shown in FIG. 1B. In the example shown in FIG. 1B, the hierarchical system has a top level (Level 0) instance, which is shown as Level 0 Instance 0 120. The top level instance may include pointers that point to lower level instances, such as Level 1 Instance 0 (122a) and Level 1 Instance K (122b). Each instance in Level 1 may point to lower level instances, such as instances shown as 124a, 124b, 124c, and 124d. Similarly, the hierarchical system may include multiple levels, such as instances 126a, 126b, and 126c in Level J. At the bottom level of the hierarchical system, shown as Level L, the instances may also be referred as leaf instances, such as Leaf Instance 0 (128a), Leaf Instance 1 (128b) and Leaf Instance N (128c). As shown in FIG. 1A and FIG. 1B, as the number of components in the system increases, the amount of data used in naming each circuit instance in the hierarchical data structure can be prohibitively large such that cost and performance of circuit simulation can be adversely affected.
Therefore, there is a need for methods and systems that address the issues of the conventional hierarchical systems described above. More specifically, there is a need for methods and systems that can effectively organize and retrieve names of instances in the hierarchical system.